1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a circuit layout of a semiconductor memory device using a magnetoresistive element as a memory cell.
2. Description of the Related Art
U.S. Pat. No. 6,587,371 discloses a magnetoresistive memory device such as a magnetoresistive memory device (MRAM), a phase-change memory device (PRAM) and ReRAM. The magnetoresistive memory device has a plurality of memory cell arrays, which are configured in such a manner that a plurality of memory cells using a magnetoresistive element is arrayed like a matrix. In the magnetoresistive memory device, different resistance states of a magnetoresistive element correspond to data “1” and “0”. For example, a low resistance state of the magnetoresistive element is defined as data “0” while a high resistance state thereof is defined as data “1”.
The magnetoresistive memory device has the following configuration. Specifically, in a data read operation from a memory cell array, a read current flows from a sense amplifier to a current sink via a select cell. In this case, a reference current flows from the sense amplifier to the current sink via a reference cell. The sense amplifier compares the read current with the reference current to determine a resistance state of the select cell.
A memory device using the foregoing magnetoresistive element needs to employ a method of carrying out data read from a memory cell array with higher precision.
Jpn. Pat. Appln. KOKAI Publication No. 2008-147437 discloses a drive layout of a magnetoresistive memory device, which is capable of reducing chip area and power consumption. Specifically, in a memory cell array, one common line is provided per two bit lines, and the common line is used in common to neighboring-column memory cells. Further, a bit line driver and a common line driver individually driving a bit line and a common line in a data write operation are arranged in a state of facing both sides of a memory cell array. Furthermore, memory cells are arrayed to be connected to different word line every column in each row of a memory cell array.